LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 78

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Bit 0
Bits 1 and 2
Bit 3
Bits 4 and 5
Bits 6 and 7
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
MODE
ONLY
BIT 3
FIFO
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the
Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the
Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this
CPU access, even if the Serial Port records new interrupts, the current indication does not change until
access is completed. The contents of the IIR are described below.
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt
is pending. When bit 0 is a logic “0”, an interrupt is pending and the contents of the IIR may be used as a
pointer to the appropriate internal service routine. When bit 0 is a logic “1”, no interrupt is pending.
These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the
Interrupt Control Table.
In non-FIFO mode, this bit is a logic “0”. In FIFO mode this bit is set along with bit 2 when a timeout
interrupt is pending.
These bits of the IIR are always logic “0”.
These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
0
0
0
BIT 2
IDENTIFICATION
0
1
1
INTERRUPT
REGISTER
BIT 1
0
1
0
BIT 0
1
0
0
Bit 7
Table 6.29 - Interrupt Control Table
0
0
1
1
PRIORIT
Y LEVEL
Highest
Second
DATASHEET
-
Bit 6
0
1
0
1
INTERRUPT SET AND RESET FUNCTIONS
Trigger Level (BYTES)
Received Data
Receiver Line
INTERRUPT
Page 78
Available
Status
TYPE
None
RCVR FIFO
14
1
4
8
Framing Error or
Break Interrupt
Overrun Error,
Receiver Data
INTERRUPT
Parity Error,
SOURCE
Available
None
Buffer or the FIFO
Reading the Line
drops below the
Status Register
Read Receiver
INTERRUPT
trigger level.
CONTROL
RESET
-
SMSC LPC47M172