LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 165

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

SMSC LPC47M172
PME_STS1
Default = 0x00
N/A
PME_EN3
Default = 0x00
on VTR POR
on VTR POR
NAME
REG OFFSET
(Type)
(R/W)
(R/W)
0x0C
0x0A
0x0B
(R)
PME Wake Status Register 1
This register indicates the state of the individual PME wake sources,
independent of the individual source enables or the PME_En bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”.
Bit[0] Reserved (Note 1)
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] SPEKEY (Wake on specific key)
Bit[6] FAN_TACH1 (note)
Bit[7] FAN_TACH2 (note)
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or HARD RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
Note:
Bits[7:0] Reserved – reads return 0
PME Wake Status Register 3
This register is used to enable individual LPC47M172 PME wake sources
onto the nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”),
if the source asserts a wake event so that the associated status bit is “1”
and the PME_En bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive
(“0”), the PME Wake Status register will indicate the state of the wake
source but will not assert the nIO_PME signal.
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] GP23
Bits[7:4] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or HARD RESET.
DATASHEET
When the GP1x/FAN_TACHx pin is configured as a GPIO (GPIO
control register bit 2 = 0), the associated PME status bit will never be
set.
When the pin is configured for the tachometer function (GPIO control
register bit 2 = 1) and then the function is switched to the GPIO
function, the associated PME status bit will be cleared.
Page 165
DESCRIPTION
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Datasheet