LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 37

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

6.3.10 I/O and DMA START Fields
6.3.11 LPC Transfers
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
SYNC Error Indication
The LPC47M172 reports errors via the LAD[3:0] = 1010 SYNC encoding.
If the host was reading data from the LPC47M172, data will still be transferred in the next two nibbles.
This data may be invalid, but it will be transferred by the LPC47M172. If the host was writing data to the
LPC47M172, the data had already been transferred.
In the case of multiple byte cycles, such as memory and DMA cycles, an error SYNC terminates the cycle.
Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first
byte, the other three bytes will not be transferred.
I/O and DMA cycles use a START field of 0000.
Reset Policy
The following rules govern the reset policy:
When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec prior to
the removal of the reset signal, so that everything is stable. This is the same reset active time after clock
is stable that is used for the PCI bus.
When nPCI_RESET goes active (low):
Wait State Requirements
I/O Transfers
The LPC47M172 inserts three wait states for an I/O read and two wait states for an I/O write cycle. A
SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would
normally be deasserted in an ISA transfer (i.e., EPP or IrCC transfers) in which case the sync pattern of
0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of
10us).
DMA Transfers
The LPC47M172 inserts three wait states for a DMA read and four wait states for a DMA write cycle. A
SYNC of 0101 is used for all DMA transfers.
See the example timing for the LPC cycles in the “Timing Diagrams” section.
the host drives the nLFRAME signal high, tristates the LAD[3:0] signals, and ignores the nLDRQ
signal.
the LPC47M172 ignores nLFRAME, tristate the LAD[3:0] pins and drive the nLDRQ signal inactive
(high).
DATASHEET
Page 37
Advanced I/O Controller with Motherboard GLUE Logic
SMSC LPC47M172
Datasheet