LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 80

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Note:
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
6.28.8 Modem Control Register (MCR)
Bit 0
Bit 1
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
Parity Enable bit. When bit 3 is a logic “1”, a parity bit is generated (transmit data) or checked (receive
data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to
generate an even or odd number of 1s when the data word bits and the parity bit are summed).
Even Parity Select bit. When bit 3 is a logic “1” and bit 4 is a logic “0”, an odd number of logic “1”’s is
transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic “1” and bit 4 is a logic
“1” an even number of bits is transmitted and checked.
This bit is the Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or
Space Parity. When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as a 0 (Space
Parity). If bits 3 and 5 are 1 and bit 4 is a 0, then the Parity bit is transmitted and checked as 1 (Mark
Parity). If bit 5 is 0 Stick Parity is disabled.
Set Break Control bit. When bit 6 is a logic “1”, the transmit data output (TXD) is forced to the Spacing or
logic “0” state and remains there (until reset by a low level bit 6) regardless of other transmitter activity.
This feature enables the Serial Port to alert a terminal in a communications system.
Divisor Latch Access bit (DLAB). It must be set high (logic “1”) to access the Divisor Latches of the Baud
Rate Generator during read or write operations. It must be set low (logic “0”) to access the Receiver Buffer
Register, the Transmitter Holding Register, or the Interrupt Enable Register.
Address Offset = 4H, DLAB = X, READ/WRITE
This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The
contents of the MODEM control register are described below.
This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic “1”, the nDTR output
is forced to a logic “0”. When bit 0 is a logic “0”, the nDTR output is forced to a logic “1”.
This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical
to that described above for bit 0.
BIT 2
0
1
1
1
1
WORD LENGTH
DATASHEET
5 bits
6 bits
7 bits
8 bits
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NUMBER OF
STOP BITS
1.5
1
2
2
2
SMSC LPC47M172