MT28C3212P2 Micron Semiconductor Products, Inc., MT28C3212P2 Datasheet - Page 11

• Manufacturer Part Number: MT28C3212P2
• Description: 2 Meg X 16 Page Flash, 128K X 16 SRAM Combo Memory, 66-ball Fbga
• Manufacturer: Micron Semiconductor Products, Inc.

FLASH MEMORY OPERATING MODES
COMMAND STATE MACHINE
chine (CSM) using standard microprocessor write tim-
ings. The CSM acts as an interface between external
microprocessors and the internal write state machine
(WSM). The available commands are listed in Table 4,
their definitions are given in Table 5 and their descrip-
tions in Table 6. Program and erase algorithms are au-
tomated by the on-chip WSM. Table 7 shows the CSM
transition states. Once a valid PROGRAM/ERASE com-
mand is entered, the WSM executes the appropriate
algorithm, which generates the necessary timing sig-
nals to control the device internally. A command is
valid only if the exact sequence of WRITEs is completed.
After the WSM completes its task, the write state ma-
chine status (WSMS) bit (SR7) (see Table 9) is set to a
logic HIGH level (V
the full command set again.
OPERATIONS
dard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/O pins DQ0–DQ7. The number of bus cycles required
to activate a command is typically one or two. The first
operation is always a WRITE. Control pins F_CE# and
F_WE# must be at a logic LOW level (V
and F_RP# must be at logic HIGH (V
operation, when needed, can be a WRITE or a READ
depending upon the command. During a READ opera-
tion, control pins F_CE# and F_OE# must be at a logic
LOW level (V
HIGH (V
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
Commands are issued to the command state ma-
Device operations are selected by entering a stan-
IH
).
IL
COMMAND DQ0–DQ7
), and F_WE# and F_RP# must be at logic
Command State Machine Codes For Device Mode Selection
IH
), allowing the CSM to respond to
10h/40h
B0h
C0h
D0h
20h
50h
60h
70h
90h
98h
FFh
IH
IL
). The second
), and F_OE#
CODE ON DEVICE MODE
Program setup/alternate program setup
Block erase setup
Clear status register
Protection configuration setup
Read status register
Read protection configuration register
Read query
Program/erase suspend
Protection register program/lock
Program/erase resume - erase confirm
Read array
Table 4
11
128K x 16 SRAM COMBO MEMORY
modes: write, read, reset, standby, and output disable.
cuitry initializes the chip to a read array mode of opera-
tion. Changing the mode of operation requires that a
command code be entered into the CSM. For each one
of the two flash memory partitions, an on-chip status
register is available. These two registers allow the moni-
toring of the progress of various operations that can
take place on a memory bank. One of the two status
registers is interrogated by entering a READ STATUS
REGISTER command onto the CSM (cycle 1), specify-
ing an address within the memory partition boundary,
and reading the register data on I/O pins DQ0–DQ7
(cycle 2). Status register bits SR0-SR7 correspond to
DQ0–DQ7 (see Table 9).
COMMAND DEFINITION
the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 5 for the CSM command defini-
tions and data for each of the bus cycles.
STATUS REGISTER
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling F_OE# and F_CE# and reading the result-
ing status code on I/O pins DQ0–DQ7. The high-order
I/Os (DQ8–DQ15) are set to 00h internally, so only the
Table 8 illustrates the bus operations for all the
When the device is powered up, internal reset cir-
Once a specific command code has been entered,
The status register allows the user to determine
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2 MEG x 16 PAGE FLASH
©2002, Micron Technology, Inc.