MT28C3212P2 Micron Semiconductor Products, Inc., MT28C3212P2 Datasheet - Page 29

• Manufacturer Part Number: MT28C3212P2
• Description: 2 Meg X 16 Page Flash, 128K X 16 SRAM Combo Memory, 66-ball Fbga
• Manufacturer: Micron Semiconductor Products, Inc.

STANDBY MODE
HIGH level on F_CE# and F_RP# to enter the standby
mode. In the standby mode, the outputs are placed in
High-Z. Applying a CMOS logic HIGH level on F_CE#
and F_RP# reduces the current to I
device is deselected during an ERASE operation or dur-
ing programming, the device continues to draw cur-
rent until the operation is complete.
AUTOMATIC POWER SAVE MODE (APS)
ods when the Flash array is not being read and the
device is in the active mode. During this time the de-
vice switches to the automatic power save (APS) mode.
When the device switches to this mode, I
to I
other operation is initiated. In this mode, the I/O pins
retain the data from the last memory address read un-
til a new address is read. This mode is entered auto-
matically if no address or control pins toggle.
V
VOLTAGES
system programming and erase with V
2.2V range (V
ing, the V
absolute hardware write protection of all blocks in the
Flash device. When V
ERASE operation results in an error, prompting the cor-
responding status register bit (SR3) to be set.
system programming and erase with V
2.2V range (V
of 100 cycles and 10 cumulative hours. The device
can withstand 100,000 WRITE/ERASE operations when
V
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
PP
PP
Icc supply current is reduced by applying a logic
Substantial power savings are realized during peri-
The MT28C3212P2FL Flash memory provides in-
The MT28C3212P2NFL Flash memory provides in-
V
CC
= V
/V
PP
2
CC
. The low level of power is maintained until an-
CC
at 12V ±5% (V
.
PP
PROGRAM AND ERASE
programming voltage can be held LOW for
PP
PP
1
1
). In addition to the flexible block lock-
).
PP
PP
is below V
2
) is supported for a maximum
PPLK
, any PROGRAM or
CC
2
PP
PP
(MAX). If the
CC
in the 0.9V–
in the 0.0V–
is reduced
29
128K x 16 SRAM COMBO MEMORY
monitors the V
tions are allowed only when V
specified in Table 12.
WRITE/ERASE operation is prevented.
DEVICE RESET
be asserted (RST# = V
reset, the device can be accessed for a READ operation
with a delayed access time of
of RST#. The circuitry used for generating the RST#
signal needs to be common with the rest of the system
reset to ensure that correct system initialization occurs.
Please refer to the timing diagram for further details.
POWER-UP SEQUENCE
to properly initialize the device:
DEVICE
MT28C3212P2FL
MT28C3212P2NFL
During WRITE and ERASE operations, the WSM
When V
To correctly reset the device, the RST# signal must
The following power-up sequence must be observed
• RST# must be at V
• Power on V
• Wait 2µS after V
• Take RST# from V
• The RST# transition from V
than 10µS.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CC
2 MEG x 16 PAGE FLASH
is below V
PP
CC
V
voltage level. WRITE/ERASE opera-
/V
PP
CC
Table 12
CC
Ranges (V)
IL
Q (V
IL
) for a minimum of
IL
MIN
IN-SYSTEM
LKO
reaches V
0.9
0.0
.
to V
CC
or V
t
RWH from the rising edge
IH
.
PP
MAX
V
PP
2.2
2.2
IL
CC
is within the ranges
CC
is below V
Q at all times).
to V
(MIN).
IH
©2002, Micron Technology, Inc.
IN-FACTORY
MIN
11.4
11.4
must be less
t
RP. After
PPLK
MAX
12.6
12.6
, any