ST72F321J ST Microelectronics, ST72F321J Datasheet - Page 117

• Manufacturer Part Number: ST72F321J
• Description: 8-BIT MCU
• Manufacturer: ST Microelectronics

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DataSheet
I
10.7.5 Low Power Modes
10.7.6 Interrupts
Figure 64. Event Flags and Interrupt Generation
Note: The I
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bit in the CC reg-
ister is reset (RIM instruction).
2
WAIT
HALT
10-bit Address Sent Event (Master mode)
End of Byte Transfer Event
Address Matched Event (Slave mode)
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
Stop Detection Event (Slave mode)
Arbitration Lost Event (Multimaster configuration)
Bus Error Event
C BUS INTERFACE (Cont’d)
Mode
4
*
U
EVF can also be set by EV6 or an error from the SR2 register.
STOPF
ADD10
.com
BERR
ARLO
ADSL
*
BTF
No effect on I
I
I
In HALT mode, the I
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
2
2
SB
AF
2
C interrupts cause the device to exit from WAIT mode.
C registers are frozen.
C interrupt events are connected to
2
C interface.
Interrupt Event
2
C interface is inactive and does not acknowledge data on the bus. The I
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ITE
Description
STOPF
ADD10
ADSEL
BERR
Event
ARLO
Flag
BTF
SB
AF
Control
Enable
ITE
Bit
INTERRUPT
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EVF
from
Wait
Exit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2
ST72321J
C interface
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from
Exit
Halt
No
No
No
No
No
No
No
No
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