ST72F321J ST Microelectronics, ST72F321J Datasheet - Page 86

• Manufacturer Part Number: ST72F321J
• Description: 8-BIT MCU
• Manufacturer: ST Microelectronics

www.DataSheet4U.com
DataSheet
ST72321J
10.5 SERIAL PERIPHERAL INTERFACE (SPI)
10.5.1 Introduction
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves however the SPI
interface can not be a master in a multi-master
system.
10.5.2 Main Features
Figure 51. Serial Peripheral Interface Block Diagram
86/179
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
Six master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun
flags
MOSI
MISO
CPU
SCK
4
SS
U
/2 max. slave mode frequency
.com
SOD
bit
SPIDR
8-Bit Shift Register
Read Buffer
SERIAL CLOCK
CPU
GENERATOR
CONTROL
MASTER
www.DataSheet4U.com
/4 max.)
Data/Address Bus
Read
Write
10.5.3 General Description
Figure 51
(SPI) block diagram. There are 3 registers:
The SPI is connected to external devices through
3 pins:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
– SS: Slave select:
put by SPI slaves
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
7
SPIE
SPIF WCOL
7
SPE
shows the serial peripheral interface
CONTROL
SPR2
OVR
STATE
SPI
Interrupt
request
MODF
MSTR
CPOL
0
www.DataSheet
www.DataSheet
www.DataSheet
www.DataSheet4U
CPHA
SOD
SS
SPICR
SPICSR
SSM
SPR1
0
1
SPR0
SSI
0
0
4U
4U.com
4U
.com
.com
.com