ST72F321J ST Microelectronics, ST72F321J Datasheet - Page 64

• Manufacturer Part Number: ST72F321J
• Description: 8-BIT MCU
• Manufacturer: ST Microelectronics

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DataSheet
ST72321J
PWM AUTO-RELOAD TIMER (Cont’d)
PWM CONTROL REGISTER (PWMCR)
Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:4 = OE[3:0] PWM Output Enable
These bits are set and cleared by software. They
enable or disable the PWM output channels inde-
pendently acting on the corresponding I/O pin.
0: PWM output disabled.
1: PWM output enabled.
Bit 3:0 = OP[3:0] PWM Output Polarity
These bits are set and cleared by software. They
independently select the polarity of the four PWM
output signals.
Note: When an OPx bit is modified, the PWMx out-
put signal polarity is immediately reversed.
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OE3
Counter <= OCRx
7
4
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OE2
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1
0
PWMx output level
OE1
OE0
Counter > OCRx
OP3
0
1
OP2
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OP1
OPx
OP0
0
1
0
DUTY CYCLE REGISTERS (PWMDCRx)
Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = DC[7:0] Duty Cycle Data
These bits are set and cleared by software.
A PWMDCRx register is associated with the OCRx
register of each PWM channel to determine the
second edge location of the PWM signal (the first
edge location is common to all channels and given
by the ARTARR register). These PWMDCR regis-
ters allow the duty cycle to be set independently
for each PWM channel.
DC7
7
DC6
DC5
DC4
DC3
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DC2
DC1
DC0
0
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