ST72F321J ST Microelectronics, ST72F321J Datasheet - Page 22

• Manufacturer Part Number: ST72F321J
• Description: 8-BIT MCU
• Manufacturer: ST Microelectronics

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DataSheet
ST72321J
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in
For more details, refer to dedicated parametric
section.
Main features
Figure 9. Clock, Reset and Supply Block Diagram
22/179
Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator)
Reset Sequence Manager (RSM)
Multi-Oscillator Clock Management (MO)
– 5 Crystal/Ceramic resonator oscillators
– 1 External RC oscillator
– 1 Internal RC oscillator
System Integrity Management (SI)
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
RESET
OSC2
OSC1
4
capability for monitoring the main supplyClock
Security System (CSS) with Clock Filter and
Backup Safe Oscillator (enabled by option
V
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Figure
OSCILLATOR
RESET SEQUENCE
MULTI-
(MO)
MANAGER
(RSM)
9.
f
OSC
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(option)
PLL
f
OSC2
SICSR
SYSTEM INTEGRITY MANAGEMENT
0
CLOCK SECURITY SYSTEM
AVD AVD LVD
IE
CLOCK
FILTER
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f
Caution: The PLL is not recommended for appli-
cations where timing accuracy is required. See
“PLL Characteristics” on page 148.
Figure 8. PLL Block Diagram
f
OSC
AVD Interrupt Request
AUXILIARY VOLTAGE
F
byte)
LOW VOLTAGE
(CSS)
RF
DETECTOR
DETECTOR
(AVD)
(LVD)
0
SAFE
OSC
PLL x 2
CSS
IE
/ 2
CSS Interrupt Request
OSC2 =
CSS
D
WDG
f
RF
OSC2
f
OSC
PLL OPTION BIT
/2.
CLOCK (MCC/RTC)
WITH REALTIME
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0
1
TIMER (WDG)
CONTROLLER
MAIN CLOCK
WATCHDOG
OSC2
f
OSC2
of 4 to 8
f
CPU
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