ST72F321J ST Microelectronics, ST72F321J Datasheet - Page 24

• Manufacturer Part Number: ST72F321J
• Description: 8-BIT MCU
• Manufacturer: ST Microelectronics

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DataSheet
ST72321J
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application
(see
Figure 11. Reset Block Diagram
24/179
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Active Phase depending on the RESET source
256 or 4096 CPU clock cycle delay (selected by
option byte)
RESET vector fetch
RESET
4
Section 14.1 on page
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Figure
10:
V
Figure
169).
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ON
11:
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Filter
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 10. RESET Sequence Phases
6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
“CONTROL
page 158
A RESET signal originating from an external
source must have a duration of at least t
order to be recognized (see
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
GENERATOR
PULSE
Active Phase
for more details.
PIN
256 or 4096 CLOCK CYCLES
INTERNAL RESET
RESET
CHARACTERISTICS”
ON
weak pull-up resistor.
WATCHDOG RESET
LVD RESET
Figure
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INTERNAL
RESET
12). This de-
VECTOR
h(RSTL)in
FETCH
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in
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