ST72F321J ST Microelectronics, ST72F321J Datasheet - Page 41

• Manufacturer Part Number: ST72F321J
• Description: 8-BIT MCU
• Manufacturer: ST Microelectronics

www.DataSheet4U.com
DataSheet
POWER SAVING MODES (Cont’d)
8.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
8.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see
10.2 on page 55
register).
The MCU can exit ACTIVE-HALT mode on recep-
tion of an MCC/RTC interrupt or a RESET. When
exiting ACTIVE-HALT mode by means of an MCC/
RTC interrupt, no 256 or 4096 CPU cycle delay oc-
curs. The CPU resumes operation by servicing the
interrupt or by fetching the reset vector which
woke it up (see
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10b’ to enable in-
terrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
CAUTION: When exiting ACTIVE-HALT mode fol-
lowing an MCC/RTC interrupt, OIE bit of MCCSR
register must not be cleared before t
MCCSR
OIE bit
0
1
4
U
.com
HALT mode
ACTIVE-HALT mode
Power Saving Mode entered when HALT
Figure
for more details on the MCCSR
instruction is executed
25).
www.DataSheet4U.com
DELAY
Section
after
the interrupt occurs (t
lay depending on option byte). Otherwise, the ST7
enters HALT mode for the remaining t
od.
Figure 24. ACTIVE-HALT Timing Overview
Figure 25. ACTIVE-HALT Mode Flow-chart
Notes:
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
3. Only the MCC/RTC interrupt can exit the MCU
from ACTIVE-HALT mode.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
[MCCSR.OIE=1]
INSTRUCTION
RUN
HALT INSTRUCTION
N
(MCCSR.OIE=1)
HALT
ACTIVE
INTERRUPT
HALT
Y
256 OR 4096 CPU
CYCLE DELAY
3)
INTERRUPT
DELAY
RESET
OR
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
FETCH RESET VECTOR
N
= 256 or 4096 t
CYCLE DELAY
www.DataSheet
www.DataSheet
www.DataSheet
www.DataSheet4U
RESET
Y
1)
VECTOR
FETCH
2)
ST72321J
DELAY
RUN
XX
XX
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
10
CPU
4)
4)
41/179
peri-
4U
4U.com
de-
4U
.com
.com
.com