ST72F321J ST Microelectronics, ST72F321J Datasheet - Page 28

• Manufacturer Part Number: ST72F321J
• Description: 8-BIT MCU
• Manufacturer: ST Microelectronics

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DataSheet
ST72321J
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Clock Security System (CSS)
The Clock Security System (CSS) protects the
ST7 against breakdowns, spikes and overfrequen-
cies occurring on the main clock source (f
is based on a clock filter and a clock detection con-
trol with an internal safe oscillator (f
6.4.3.1 Clock Filter Control
The PLL has an integrated glitch filtering capability
making it possible to protect the internal clock from
overfrequencies created by individual spikes. This
feature is available only when the PLL is enabled.
If glitches occur on f
connection or noise), the CSS filters these auto-
matically, so the internal CPU frequency (f
continues deliver a glitch-free signal
15).
6.4.3.2 Clock detection Control
If the clock signal disappears (due to a broken or
disconnected resonator...), the safe oscillator de-
livers a low frequency clock signal (f
allows the ST7 to perform some rescue opera-
tions.
Automatically, the ST7 clock source switches back
from the safe oscillator (f
source (f
When the internal clock (f
oscillator (f
fied by hardware setting the CSSD bit in the SIC-
SR register. An interrupt can be generated if the
Figure 15. Clock Filter Function
28/179
Clock Filter Function
Clock Detection Function
4
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OSC
f
f
f
f
f
OSC2
CPU
OSC2
SFOSC
CPU
SFOSC
) recovers.
), the application software is noti-
OSC
(for example, due to loose
CPU
SFOSC
) is driven by the safe
) if the main clock
SFOSC
SFOSC
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(see Figure
).
OSC
) which
CPU
). It
)
CSSIE bit has been previously set.
These two bits are described in the SICSR register
description.
6.4.4 Low Power Modes
6.4.4.1 Interrupts
The CSS or AVD interrupt events generate an in-
terrupt if the corresponding Enable Control Bit
(CSSIE or AVDIE) is set and the interrupt mask in
the CC register is reset (RIM instruction).
WAIT
HALT
CSS event detection
(safe oscillator acti-
vated as main clock)
AVD event
Mode
Interrupt Event
No effect on SI. CSS and AVD interrupts
cause the device to exit from Wait mode.
The CRSR register is frozen.
The CSS (including the safe oscillator) is
disabled until HALT mode is exited. The
previous CSS configuration resumes when
the MCU is woken up by an interrupt with
“exit from HALT mode” capability or from
the counter reset value when the MCU is
woken up by a RESET.
Event
CSSD
AVDF
Flag
Description
Control
Enable
CSSIE
AVDIE
Bit
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from
Wait
Exit
Yes
Yes
from
Halt
Exit
No
No
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