L64118 LSI Logic Corporation, L64118 Datasheet - Page 23

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

Channel Interface Port
Table 4
1. A few cycles after reset (RESETn is driven HIGH), the L64118 initiates a
These signals provide the physical connection to Channel Interface
devices, such as LSI Logic’s L64724 or L64768. This port supports both
parallel and serial connections.
CCLK
CDATA[7:0]
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 23
Signal
TTXREQ/GPIO12
TTXDATA
TXD0/2
TXD1/ICE_TX
VVALID
WRn
transaction on the EBus, changing some of the default values in this table.
Default Values for L64118 Output and Bidirectional
Signals After Reset
Channel Clock
When CVALID is asserted HIGH, the L64118 latches
CDATA[7:0] on the rising edge of CCLK. In serial mode,
the L64118 uses only CDATA[0]. In serial mode, the
maximum clock rate is 60 MHz; in parallel mode, it is
13 MHz. The CCLK must toggle during reset to ensure
proper reset of the channel interface block.
Channel Data
These signals deliver channel information to the L64118.
When CVALID is asserted, the chip latches the data on
every rising edge of CCLK. When the L64118 is in
parallel input mode, all CDATA[7:0] signals deliver data.
When the L64118 is in serial mode, only CDATA[0]
delivers data.
Default Value
floating
not asserted
asserted
not asserted
not asserted
1
(Cont.)
Notes
behaves as an input
Input
Input