L64118 LSI Logic Corporation, L64118 Datasheet - Page 4
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L64118
Manufacturer Part Number
L64118
Description
Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
Manufacturer
LSI Logic Corporation
Datasheet
1.L64118.pdf
(68 pages)
- Current page: 4 of 68
- Download datasheet (550Kb)
Features
Channel
Demux
4
The 27 MHz system clock drives the L64118 internal demultiplexer block,
as well as most of the peripheral modules. The PLL block generates
54 MHz from the 27 MHz system clock to drive the CPU logic.
The L64118 includes four DMA channels (one dedicated to the
IEEE1284 port, three independent) that can be used to transfer data
between peripheral ports and memory, from one memory location to
another, or from memory to an external system device.
The L64118 provides additional system features for a set-top box
application, including:
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
Compliance with ISO/IEC 13818-1 (MPEG-2) Transport
specifications
Sustained rates up to 90 Mbits/s serial and up to 13.0 Mbytes/s
parallel transport stream input interface
Direct interface to LSI Logic single-chip channel decoder devices,
such as the L64704, the L64768, and the L64724
PID filtering (32 user-programmable PIDs)
–
–
–
Support of a Program Clock Reference (PCR) PID
CRC32 in parallel to all sections in the filtering process
Descrambler core compliant to DVB common scrambling
specifications
Support for transport-level and PES-level descrambling
Seamless support of scrambled and unscrambled data
Support of up to 12 pairs of 64-bit keys
Hardware-assisted section filtering for 30 general-purpose PIDs
(PSI, SI, and Private)
Each filter includes 12 match bytes and 12 mask bytes
Each PID can select up to 32 filters simultaneously
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