L64118 LSI Logic Corporation, L64118 Datasheet - Page 33

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

SDRAM Interface
TXD2
The following group of signals provides the interface between the L64118
and external SDRAM devices. The SDRAM interface works with
PC66/100 compliant SDRAMs. The L64118 SDRAM interface runs at 54
MHz and is capable of accessing 2, 4, 8, or 16 Mbyte memory
configurations using 16 Mbit or 64 Mbit devices.
This interface has a 16-bit data bus (SBD[15:0]). The upper and lower
byte mask signals (SDQMH and SDQML) control halfword and byte
accesses. The SBA[1:0] outputs support two- and four-bank SDRAM
devices. The L64118 automatically performs SDRAM refreshes.
The L64118 does not support the Chip Select (CSn) and Clock Enable
(CKE) signals. Tie these SDRAM signals active LOW and HIGH,
respectively, on the SDRAM device(s) used.
SA[11:0]
SBA[1:0]
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 33
Transmit Data - Serial ICEPort
If GPIO[43] is sampled LOW during reset, this pin serves
as ICE_TX, the serial ICE transmit data output port. By
default, this signal is not asserted after reset.
Transmit Data Port 2
This signal outputs data in compliance with the RS232
protocol’s asynchronous specification. The data rate on
this pin is determined by programming the SIO Baud
Rate register. Data transmitted on TXD2 comes from the
Transmit register of Port 2. By default, this signal is not
asserted after reset.
SDRAM Address Bus
These signals carry the 12-bit SDRAM address bus. The
number of row and column address bits used is
programmable in the SDRAM Configuration register.
SDRAM Bank Select
These signals allow access to SDRAM devices with
either two or four banks. The number of bank select bits
used is programmable in the SDRAM Configuration
register.
Output
Output
Output
Output