L64118 LSI Logic Corporation, L64118 Datasheet - Page 39

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

BUSY/AUXSB
FAULTn/AUXCLK
INIT/AUXPID[2]
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 39
1284 - Peripheral Busy
In 1284 mode, this signal functions as BUSY. When this
signal is HIGH, the 1284 port is not ready for a data
transfer. By default, this signal is not asserted after reset.
Aux - Sync Byte
In Aux mode, this signal functions as AUXSB to indicate
that the data being sent through the auxiliary port is the
first byte (sync byte) of a transport packet.
GPIO15
This signal can serve as a general-purpose I/O signal
(GPIO15) by setting bit 3 in the General-Purpose Mode
register.
1284 - Peripheral Fault Operation
In 1284 mode, this signal functions as FAULTn. This
signal indicates that the 1284 port encountered an error
during operation. Typically, this error is due to overrun,
underrun, or parity error.
Aux - Aux Port Clock
In Aux mode, this signal functions as AUXCLK, which is
the reference clock for all transactions on the auxiliary
port. When the Aux port is configured as an output port,
this signal is an output with programmable frequencies of
13.5, 6.75 and 3.375 MHz. When the Aux port is
configured as an input port, this signal is an input with a
frequency based on the input transport stream data rate.
GPIO24
This signal can also serve as a general-purpose I/O
signal (GPIO24) by setting bit 3 in the General-Purpose
Mode register.
1284 - Peripheral Initialization
In 1284 mode, this signal functions as INITn. When reset
LOW, this signal resets the IEEE1284 port and returns
the logic to the compatibility and idle state.
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Input