L64118 LSI Logic Corporation, L64118 Datasheet - Page 25

• Manufacturer Part Number: L64118
• Description: Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
• Manufacturer: LSI Logic Corporation

External System Bus (EBus)
PLLVSS
The EBus comprises a 32-bit wide interface with multiplexed address and
data. Eight address bits are available as demultiplexed bits for an easy
interface to devices that do not need the full address space. All bus
transactions are synchronous to the 27 MHz output CPU_CLK.
A subset of these signals can be programmed to act as general-purpose
I/O signals by setting bit [0] in the General-Purpose Mode register.
AD[31:0]
ADDR[7:0]
ALE
BEn[1:0]
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 25
PLL Analog VSS
This provides a separate ground to the PLL circuit
through PLLVSS so that switching noise from the digital
portion of the chip does not affect PLL stability.
Multiplexed Address/Data Bus
AD[31:0] is the multiplexed address/data bus. The
L64118 can be programmed to drive the full address on
this bus at access start. After this address phase the bus
presents write data for a write or the external device
drives data on the bus in a read.
Address Latch Enable
This active HIGH signal controls the latches for
demultiplexing the address from the AD bus.
Byte Enables
The four byte enable outputs are asserted during a read
or write transaction on the EBus to control which of the
four byte lanes are enabled. The byte lane selection is
dependent on the width of the transaction (word,
halfword, or byte) and the data width of the external
device (32, 16, or 8 bits).
Demuxed Address Bus
ADDR[7:0] provides eight bits of demultiplexed address
bits. This bus allows some designs to remove the
external address latch on the multiplexed address/data
bus to hold the address throughout the transaction. The
EBus uses byte addressing. All 16-bit devices must
ignore ADDR[0]. All 32-bit devices must ignore
ADDR[1:0].
Bidirectional
Output
Output
Output
Input