L64118 LSI Logic Corporation, L64118 Datasheet - Page 27
L64118
Manufacturer Part Number
L64118
Description
Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
Manufacturer
LSI Logic Corporation
Datasheet
1.L64118.pdf
(68 pages)
- Current page: 27 of 68
- Download datasheet (550Kb)
CSn[3:0]
CSn[4]
CSn[5]/MEMSTBn
EACKn
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 27
Programmable Chip Select
This pin is similar in function to the other five chip select
output pins. It is used to select specific external devices
according to on-chip address decoding.
GPIO1
CSn[4] can serve as a general-purpose I/O signal
(GPIO1) by setting bit 0 in the General-Purpose Mode
register.
Target Acknowledge
This signal indicates to the L64118 that the external
device is ready to complete the current read or write
cycle. The transaction will finish if both EACKn is
asserted and the internal wait state generator has
expired. This mechanism allows devices to extend an
access beyond the number of wait states programmed for
that particular address area.
EACKn can be programmed to be either active HIGH or
LOW, using the XPOS bit in the CEBUSMODE register.
EACKn must be deasserted before the next transaction
acknowledge cycle.
For self-acknowledge devices, the external EACKn pin
can be ignored, so the transaction completes when the
wait state generator expires. This is controlled by the
XACK bit in the CECFGn register.
Programmable Chip Selects
Each chip select pin can be programmed to assert in a
specific address area. These pins are used to select
specific external devices according to on-chip address
decoding. They make interfacing to various peripherals
easier, as they can remove the need for external address
decoders.
Chip Select[5] or Memory Strobe
This pin is similar in function to the other five chip select
output pins but holds the characteristic of being able to
function as the MEMSTBn (active LOW memory strobe)
signal. The MEMSTBn signal is a general-purpose
signal. It can be used to indicate that a memory
transaction is in progress. It is asserted in both read and
write cycles. The timing on this signal is programmable.
Bidirectional
Output
Output
Output
Input
Related parts for L64118
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Mpeg-2 Audio/video Decoder
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Satellite Decoder Technical Manual 5/97
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Satellite Receiver
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Tuner/receiver Chipset
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Tuner And Satellite Receiver Chipset Data Sheet 2/01
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Smatv Qam Encoder
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
DVB Qam Modulator
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Dvb-t Cofdm Demodulator Technical Manual 2/00
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
16-Bit HCMOS Multiplier / Accumulators
Manufacturer:
LSI Logic Corporation
Part Number:
Description:
Transport with Embedded CPU and Control
Manufacturer:
LSI Logic Corporation
Part Number:
Description:
32-Bit HCMOS IEEE Floating-Point Processor
Manufacturer:
LSI Logic Corporation
Part Number:
Description:
Variable-Length Video Shift Registers
Manufacturer:
LSI Logic Corporation