MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 13

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

2.2.2.1
The Status Register, shown in Register 2-1, contains:
• Arithmetic status of the ALU
• Reset status
• Bank select bits for data memory (SRAM)
The Status Register can be the destination for any
instruction, like any other register. If the Status Register
is the destination for an instruction that affects the Z,
DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
Status Register as destination may be different than
intended.
REGISTER 2-1:
 2003 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Status Register
STATUS — STATUS REGISTER (ADDRESS: 03h OR 83h)
bit 7
IRP: This bit is reserved and should be maintained as ‘0’
RP1: This bit is reserved and should be maintained as ‘0’
RP0: Register Bank Select bit (used for direct addressing)
1 = Bank 1 (80h - FFh)
0 = Bank 0 (00h - 7Fh)
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
For borrow, the polarity is reversed.
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
Legend:
R = Readable bit
- n = Value at POR
Reserved Reserved
IRP
For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low-order bit of the source register.
RP1
Advance Information
R/W-0
RP0
W = Writable bit
‘1’ = Bit is set
R-1
TO
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the Status Register as
000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
Status Register, because these instructions do not
affect any Status bits. For other instructions not affect-
ing any Status bits, see the “Instruction Set Summary”.
Note 1: Bits IRP and RP1 (STATUS<7:6>) are not
2: The C and DC bits operate as a Borrow
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-1
PD
used by the PIC12F683 and should be
maintained as clear. Use of these bits is
not recommended, since this may affect
upward compatibility with future products.
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
R/W-x
Z
PIC12F683
x = Bit is unknown
R/W-x
DC
DS41211A-page 11
R/W-x
C
bit 0