MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 43

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

5.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If TMR0 is written, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
FIGURE 5-1:
 2003 Microchip Technology Inc.
T0CKI
SWDTEN
Note:
pin
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register, WDTPS<3:0> are bits in the WDTCON register.
WDTE
(= F
CLKOUT
OSC
31 kHz
INTRC
T0SE
TIMER0 MODULE
Timer0 Operation
Additional information on the Timer0
module is available in the PICmicro
Range Reference Manual, (DS33023).
/4)
Watchdog
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Timer
T0CS
0
1
PSA
Prescaler
0
1
16-bit
Advance Information
16
®
Prescaler
WDTPS<3:0>
Mid-
8-bit
8
PS0-PS2
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of
pin GP2/T0CKI. The incrementing edge is determined
by
(OPTION_REG<4>). Clearing the T0SE bit selects the
rising edge.
5.2
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit (INTCON<2>). The interrupt
can be masked by clearing the T0IE bit (INTCON<5>).
The T0IF bit must be cleared in software by the Timer0
module Interrupt Service Routine before re-enabling
this interrupt. The Timer0 interrupt cannot wake the
processor from Sleep since the timer is shut off during
Sleep.
Note:
the
Timer0 Interrupt
Counter mode has specific external clock
requirements. Additional information on
these requirements is available in the
PICmicro
(DS33023).
PSA
PSA
source
1
0
1
0
SYNC 2
®
Cycles
Time-out
Mid-Range Reference Manual,
edge
WDT
PIC12F683
(T0SE)
Data Bus
Set Flag bit T0IF
DS41211A-page 41
8
TMR0
on Overflow
control
bit