MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 96

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

PIC12F683
12.6.4
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate in the event of
an oscillator failure. The FSCM can detect oscillator
failure at any point after the device has exited a Reset
or Sleep condition and the Oscillator Start-up Timer
(OST) has expired.
FIGURE 12-11:
The FSCM function is enabled by setting the FCMEN
bit in configuration word. It is applicable to all oscillator
options except INTOSC.
In the event of an oscillator failure, the FSCM will set
the OSFIF bit (PIR1<2>) and generate an oscillator fail
interrupt if the OSFIE bit (PIE1<2>) is set. The device
will then switch the system clock to the INTOSC. The
system will continue to come from the INTOSC unless
the primary oscillator recovers and the Fail-Safe
condition is exited.
The frequency of the internal oscillator will depend
upon
(OSCCON<6:4>).
condition, the OSTS bit (OSCCON<3>) is automati-
cally cleared to reflect that the secondary oscillator is
active and the WDT is cleared. The SCS bit
(OSCCON<0>) is not updated.
The INTRC is enabled and the FSCM sample clock is
generated by dividing the INTRC clock by 64. This will
allow enough time between FSCM sample clocks for a
system clock edge to occur. The LTS (OSCCON<1>)
Status bit does not reflect that the INTRC is enabled.
On the rising edge of the post scaled clock, the
monitoring latch (CM = ‘0’) will be cleared. On a falling
edge of the primary system clock, the monitoring latch
will be set (CM = ‘1’). In the event that a falling edge of
the post scaled clock occurs, and the monitoring latch
is not set, a clock failure has been detected.
DS41211A-page 94
Oscillator
Note:
(~32 s)
Primary
31 kHz
INTRC
Clock
the
Two-speed
enabled when the Fail-Safe option is
enabled.
FAIL-SAFE CLOCK MONITOR
value
(~2 ms)
488 Hz
÷ 64
Upon
contained
FSCM BLOCK DIAGRAM
Start-up
(edge-triggered)
Clock Monitor
entering
Latch (CM)
C
S
in
is
Q
Q
the
the
automatically
IRCF
Advance Information
Detected
Fail-Safe
Failure
Clock
bits
12.6.4.1
The Fail-Safe condition is exited with either a Reset,
the execution of a SLEEP instruction or a modification
of the SCS bit. While in Fail-Safe mode, the
PIC12F683 uses the secondary clock, INTOSC, as the
system clock source. The IRCF bits (OSCCON<6:4>)
can be modified to adjust the INTOSC frequency with-
out exiting the Fail-Safe condition.
In this mode, the user can set the SCS bit
(OSCCON<0>) to exit the Fail-Safe condition and then
clear the SCS bit to attempt to restart the primary
oscillator. If it starts, the FSCM will be reenabled after
the OST expires. If it fails to start, the INTOSC will
continue to supply the system clock but the device will
not reenter the Fail-Safe condition.
Note:
The INTOSC will be enabled if the IRCF
(OSCCON<6:4>) selects a frequency
greater than 31KHz (IRCF<2:0>
Fail-Safe Mode
 2003 Microchip Technology Inc.
‘000’).