MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 33
MCP1726T-ADJZEMF
Manufacturer Part Number
MCP1726T-ADJZEMF
Description
Regulator, Extended Industrial, HVSON, 8-Pin|
Manufacturer
Microchip Technology
Datasheet
1.MCP1726T-ADJZEMF.pdf
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TABLE 3-4:
2003 Microchip Technology Inc.
Note 1:
LP, XT, HS,
LP, XT, HS
INTOSC
INTOSC
Current
System
EC, RC
Clock
If the IRCF<2:0> bits select 31 kHz, the LTS bit will be set after the INTRC is stable. If the IRCF<2:0> bits
select 125 kHz to 8 MHz, the HTS bit will be set after the INTOSC is stable.
FOSC<2:0> = EC
FOSC<2:0> = RC
FOSC<2:0> = LP,
CLOCK SWITCHING MODES
(Due to Reset)
Modified to:
LP, XT, HS
(INTOSC)
SCS bit
XT, HS
or
1
0
0
0
1024 Clocks
1024 Clocks
Next falling
Next falling
edge of EC
INTOSC
edge of
Delay
or RC
(OST)
(OST)
Advance Information
OSTS
bit
0
1
1
1
HTS/LTS
N/A
N/A
N/A
1
bit
(1)
LP, XT, HS
LP, XT, HS
Postscaler
INTOSC
INTOSC
System
INTRC
Clock
New
EC
RC
or
or
or
The INTOSC oscillator
frequency is dependent
upon the IRCF bits.
During the 1024 clocks,
program execution is
clocked from the secondary
oscillator until the
primary oscillator becomes
stable.
When a Reset occurs, there
is no clock transition
sequence.
Instruction execution and/or
peripheral operation is
suspended unless
Two-speed Start-up or
Fail-Safe Clock Monitor is
enabled, after which the
INTOSC will act as the sys-
tem clock until the OST
timer has expired.
PIC12F683
Comments
DS41211A-page 31
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