MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 15

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

2.2.2.3
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, GPIO change and external
GP2/INT pin interrupts.
REGISTER 2-3:
 2003 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTCON Register
INTCON — INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
INTE: GP2/INT External Interrupt Enable bit
1 = Enables the GP2/INT external interrupt
0 = Disables the GP2/INT external interrupt
GPIE: GPIO Change Interrupt Enable bit
1 = Enables the GPIO change interrupt
0 = Disables the GPIO change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: GP2/INT External Interrupt Flag bit
1 = The GP2/INT external interrupt occurred (must be cleared in software)
0 = The GP2/INT external interrupt did not occur
GPIF: GPIO Change Interrupt Flag bit
1 = When at least one of the GPIO<5:0> pins changed state (must be cleared in software)
0 = None of the GPIO<5:0> pins have changed state
Note 1:
Legend:
R = Readable bit
- n = Value at POR
R/W-0
GIE
2:
IOC register must also be enabled.
T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should
be initialized before clearing T0IF bit.
R/W-0
PEIE
Advance Information
R/W-0
T0IE
W = Writable bit
‘1’ = Bit is set
R/W-0
INTE
(2)
(1)
Note:
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
GPIE
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
R/W-0
T0IF
PIC12F683
x = Bit is unknown
R/W-0
INTF
DS41211A-page 13
R/W-0
GPIF
bit 0