MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 70

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

PIC12F683
10.1.7
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRISIO bits selected as
inputs.
To determine sample time, see Section 15.0 “Electri-
cal Specifications”. After this sample time has
elapsed the A/D conversion can be started.
These steps should be followed for an A/D conversion:
1.
2.
3.
4.
5.
6.
7.
DS41211A-page 68
Configure the A/D module:
• Configure analog/digital I/O (ANSEL)
• Configure voltage reference (ADCON0)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ANSEL)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit (PIR1<6>)
• Set ADIE bit (PIE1<6>)
• Set PEIE and GIE bits (INTCON<7:6>)
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0<0>)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
• Waiting for the A/D interrupt
Read A/D Result register pair
(ADRESH:ADRESL), clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as T
required before the next acquisition starts.
(with interrupts disabled); OR
CONFIGURING THE A/D
AD
. A minimum wait of 2 T
Advance Information
AD
is
EXAMPLE 10-1:
;This code block configures the A/D
;for polling, Vdd reference, R/C clock
;and GP0 input.
;
;Conversion start & wait for complete
;polling code included.
;
BSF
MOVLW
MOVWF
BSF
BCF
MOVLW
MOVWF
CALL
BSF
BTFSC
GOTO
MOVF
MOVWF
BSF
MOVF
MOVWF
STATUS,RP0
B’01110001’
ANSEL
TRISIO,0
STATUS,RP0
B’10000001’
ADCON0
SampleTime
ADCON0,GO
ADCON0,GO
$-1
ADRESH,W
RESULTHI
STATUS,RP0
ADRESL,W
RESULTLO
A/D CONVERSION
 2003 Microchip Technology Inc.
;Bank 1
;A/D RC clock
;Set GP0 to analog
;Set GP0 to input
;Bank 0
;Right, Vdd Vref, AN0
;Wait min sample time
;Start conversion
;Is conversion done?
;No, test again
;Read upper 2 bits
;Bank 1
;Read lower 8 bits