MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 91

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

12.4.1
External interrupt on GP2/INT pin is edge-triggered;
either rising if INTEDG bit (OPTION<6>) is set, or
falling, if INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The GP2/INT
interrupt can wake-up the processor from Sleep if the
INTE bit was set prior to going into Sleep. The status
of the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up
(0004h). See Section 12.7 “Power-Down Mode
(Sleep)” for details on Sleep and Figure 12-13 for
timing of wake-up from Sleep through GP2/INT
interrupt.
FIGURE 12-8:
 2003 Microchip Technology Inc.
INSTRUCTION FLOW
Note:
Note 1:
GIE bit
(INTCON<7>)
INTF Flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
Executed
Instruction
Fetched
PC
2:
3:
4:
5:
on
GP2/INT INTERRUPT
The ANSEL (9Fh) and CMCON0 (19h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
(3)
INTF flag is sampled here (every Q1).
Asynchronous interrupt latency = 3-4 T
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
CLKOUT is available only in INTOSC and RC Oscillator modes.
For minimum width of INT pulse, refer to AC specs.
INTF is enabled to be set any time during the Q4-Q1 cycles.
the
Q1
Inst (PC-1)
GP2/INT
Inst (PC)
INT PIN INTERRUPT TIMING
(1)
Q2
PC
Q3
(4)
pin,
Q4
(5)
Q1
the
Inst (PC+1)
Inst (PC)
Q2
(1)
Advance Information
INTF
PC+1
CY
Q3
. Synchronous latency = 3 T
bit
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
12.4.2
An overflow (FFh
set the T0IF (INTCON<2>) bit. The interrupt can
be
(INTCON<5>) bit. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
12.4.3
An input change on GPIO change sets the GPIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the GPIE (INTCON<3>)
bit. Plus, individual pins can be configured through the
IOC register.
PC+1
—
Note:
Q3
enabled/disabled
Q4
(2)
CY
TMR0 INTERRUPT
GPIO INTERRUPT
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF
interrupt flag may not get set.
, where T
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
CY
00h) in the TMR0 register will
Q3
= instruction cycle time.
by
PIC12F683
Q4
setting/clearing
Q1
DS41211A-page 89
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4
T0IE