MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 9

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

2.0
2.1
The PIC12F683 has a 13-bit program counter capable
of addressing an 8k x 14 program memory space. Only
the first 2k x 14 (0000h - 07FFh) for the PIC12F683 is
physically implemented. Accessing a location above
these boundaries will cause a wrap around within the
first 2k x 14 space. The Reset vector is at 0000h and
the interrupt vector is at 0004h (see Figure 2-1).
FIGURE 2-1:
 2003 Microchip Technology Inc.
CALL, RETURN
RETFIE, RETLW
MEMORY ORGANIZATION
Program Memory Organization
INTERRUPT VECTOR
ON-CHIP PROGRAM
RESET VECTOR
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 8
MEMORY
PC<12:0>
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F683
13
000H
0004
0005
07FFH
0800H
1FFFH
Advance Information
2.2
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the general purpose registers
and the Special Function Registers (SFR). The Special
Function Registers are located in the first 32 locations
of each bank. Register locations 20h-7Fh in Bank 0 and
A0h-BFh in Bank 1 are general purpose registers,
implemented as static RAM. Register locations F0h-
FFh in Bank 1 point to addresses 70h-7Fh in Bank 0.
All other RAM is unimplemented and returns ‘0’ when
read. RP0 (STATUS<5>) is the bank select bit.
• RP0 = ‘0’ Bank 0 is selected
• RP0 = ‘1’ Bank 1 is selected
2.2.1
The register file is organized as 128 x 8 in the
PIC12F683. Each register is accessed, either directly
or indirectly, through the File Select Register FSR (see
Section 2.4 “Indirect Addressing, INDF and FSR
Registers”).
Note:
Data Memory Organization
The IRP and RP1 bits STATUS<7:6> are
reserved
maintained as ‘0’s.
GENERAL PURPOSE REGISTER
FILE
and
PIC12F683
should
DS41211A-page 7
always
be