LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 131

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LM3S101-CRN20-XNPT

Manufacturer Part Number
LM3S101-CRN20-XNPT
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
General-Purpose Timers
9.1
Figure 9-1.
9.2
9.2.1
131
Interrupt
Timer A
Interrupt
Timer B
System
Clock
Interrupt/Config
GPTMCFG
GPTMCTL
GPTMIMR
GPTMRIS
GPTMMIS
GPTMICR
Block Diagram
Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-
bit load/ initialization registers and their associated control functions. The exact functionality of
each GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see
page 141), the TimerA Mode (GPTMTAMR) register (see page 142), and the TimerB Mode
(GPTMTBMR) register (see page 143). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all
control registers are cleared and in their default states. Counters TimerA and TimerB are initialized
to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 150) and the GPTM TimerB Interval Load (GPTMTBILR)
register (see page 151). The prescale counters are initialized to 0x00: the GPTM TimerA
Prescale (GPTMTAPR) register (see page 154) and the GPTM TimerB Prescale (GPTMTBPR)
register (see page 155).
GPTM Block Diagram
GPTMTAMATCHR
GPTMTBMATCHR
Timer A Control
Timer B Control
GPTMTAPMR
GPTMTBPMR
GPTMTAILR
GPTMTAMR
GPTMTBILR
GPTMTBMR
GPTMTAPR
GPTMTBPR
Preliminary
TA Comparator
TB Comparator
GPTMTBR
0x0000 (Down Counter Modes )
0x0000 (Down Counter Modes )
GPTMAR
En
En
RTC Divider
Clk/Edge
Clk/Edge
Detect
Detect
March 22, 2006
CCP1
32KHz

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