LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 152

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

March 22, 2006
Reset
Reset
Type
Type
GPTM TimerA Match (GPTMTAMATCHR)
Offset 0x030
31:16
R/W
R/W
31
15
0
0
15:0
Bit
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count
modes.
R/W
R/W
30
14
0
0
TAMRH
TAMRL
Name
R/W
R/W
29
13
0
0
R/W
R/W
28
12
0
0
Type
R/W
R/W
R/W
R/W
27
11
0
0
R/W
R/W
26
10
0
0
0xFFFF
0xFFFF
0x0000
(32-bit
mode)
(16-bit
mode)
Reset
R/W
R/W
25
0
9
0
Preliminary
Description
GPTM TimerA Match Register High
When configured for 32-bit Real-Time Clock (RTC) mode via
the GPTMCFG register, this value is compared to the upper
half of GPTMTAR, to determine match events.
In 16-bit mode, this field reads as 0 and does not have an effect
on the state of GPTMTBMATCHR.
GPTM TimerA Match Register Low
When configured for 32-bit Real-Time Clock (RTC) mode via
the GPTMCFG register, this value is compared to the lower half
of GPTMTAR, to determine match events.
When configured for PWM mode, this this value along with
GPTMTAILR, determines the duty cycle of the output PWM
signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted.
The total number of edge events counted is equal to the value
in GPTMTAILR minus this value.
R/W
R/W
24
0
8
0
TAMRH
TAMRL
R/W
R/W
23
0
7
0
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
LM3S101 Data Sheet
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0
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