LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 21

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Architectural Overview
1.4
1.4.1
1.4.1.1
1.4.1.2
1.4.2
1.4.2.1
1.4.3
1.4.3.1
21
Functional Overview
The following sections provide an overview of the features of the LM3S101 microcontroller. The
chapter number in parenthesis indicates where that feature is discussed in detail. Ordering and
support information can be found in “Contact Information” on page 506.
ARM Cortex™-M3
Processor Core (Section 2 on page 26)
All members of the Stellaris product family, including the LM3S101 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core
for a high-performance, low-cost platform that meets the needs of minimal memory
implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
Section 2, “ARM Cortex-M3 Processor Core,” on page 26 provides an overview of the ARM core;
the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual.
Nested Vectored Interrupt Controller (NVIC)
The LM3S101 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed
without the overhead of state saving and restoration. Software can set eight priority levels on
seven exceptions (system handlers) and 14 interrupts.
Section 4, “Interrupts,” on page 31 provides an overview of the NVIC controller and the interrupt
map. Exceptions and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference
Manual.
Motor Control Peripherals
To enhance motor control, the LM3S101 controller features Pulse Width Modulation (PWM)
outputs.
PWM (“16-Bit PWM Mode” on page 139)
Pulse Width Modulation (PWM) is a powerful technique often used to regulate a voltage by holding
the frequency constant and varying the pulse width.
On the LM3S101, PWM motion control functionality can be achieved through the motion control
features of the general-purpose timers (using the CCP pins).
The General-Purpose Timer Module’s CCP (Capture Compare PWM) pins are software
programmable to support a simple PWM mode with a software-programmable output inversion of
the PWM signal.
Analog Peripherals
To handle analog signals, the LM3S101 controller offers two analog comparators.
Analog Comparators (Section 13 on page 251)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
Preliminary
March 22, 2006