LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 5

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

List of Figures
Figure 1-1.
Figure 1-2.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 11-1.
Figure 11-2.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 12-6.
Figure 12-7.
Figure 12-8.
Figure 12-9.
Figure 12-10. National Semiconductor MICROWIRE Frame Format (Single Frame) ................................... 225
Figure 12-11. National Semiconductor MICROWIRE Frame Format (Continuous Transfers) ...................... 226
Figure 12-12. National Semiconductor MICROWIRE Frame Format, SSIFss Input Setup
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 14-1.
Figure 17-1.
Figure 17-2.
Figure 17-3.
Figure 17-4.
Figure 17-5.
Figure 17-6.
5
Stellaris High-Level Block Diagram ........................................................................................... 20
Stellaris System-Level Block Diagram....................................................................................... 25
CPU High-Level Block Diagram ............................................................................................... 27
TPIU Block Diagram .................................................................................................................. 28
JTAG Module Block Diagram .................................................................................................... 35
Test Access Port State Machine ............................................................................................... 38
IDCODE Register Format.......................................................................................................... 42
BYPASS Register Format ......................................................................................................... 42
Boundary Scan Register Format ............................................................................................... 43
External Circuitry to Extend Reset............................................................................................. 45
Main Clock Tree ........................................................................................................................ 48
Flash Block Diagram ................................................................................................................. 80
GPIO Module Block Diagram .................................................................................................... 94
GPIO Port Block Diagram.......................................................................................................... 95
GPIODATA Write Example........................................................................................................ 95
GPTM Block Diagram.............................................................................................................. 131
16-Bit Input Edge Count Mode Example ................................................................................. 135
16-Bit Input Edge Time Mode Example................................................................................... 136
16-Bit PWM Mode Example .................................................................................................... 137
UART Block Diagram .............................................................................................................. 183
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 222
Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 223
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 223
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 224
Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 224
Analog Comparator Block Diagram ......................................................................................... 251
Structure of Comparator Unit................................................................................................... 252
Pin Connection Diagram.......................................................................................................... 262
GPIODATA Read Example ....................................................................................................... 96
Watchdog Timer Block Diagram.............................................................................................. 160
UART Character Frame........................................................................................................... 184
SSI Block Diagram .................................................................................................................. 218
TI Synchronous Serial Frame Format (Single Transfer).......................................................... 220
TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 221
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 222
and Hold Requirements........................................................................................................... 227
Comparator Internal Reference Structure ............................................................................... 253
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ................ 275
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer................................. 276
SSI Timing for SPI Frame Format (FRF=00), with SPH=1...................................................... 276
JTAG Test Clock Input Timing................................................................................................. 277
JTAG Boundary Scan Timing .................................................................................................. 278
JTAG Test Access Port (TAP) Timing ..................................................................................... 278
Preliminary
March 22, 2006