LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 49

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

System Control
6.1.4.5
6.1.5
6.2
Table 6-1.
49
Offset
Device Identification and Capabilities
0x000
0x004
0x008
0x010
0x014
Name
DID0
DID1
DC0
DC1
DC2
changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC register is switched to use the PLL.
Clock Verification Timers
There are three identical clock verification circuits that can be enabled though software. The circuit
checks the faster clock by a slower clock using timers:
If the verification timer function is enabled and a failure is detected, the main clock tree is
immediately switched to a working clock and an interrupt is generated to the controller. Software
can then determine the course of action to take. The actual failure indication and clock switching
does not clear without a write to the CLKVCLR register, an external reset, or a POR reset. The
clock verification timers are controlled by the PLLVER, BOSCVER, and MOSCVER bits in the RCC
register (see page 70).
System Control
For power-savings purposes, the RCGCn, SCGCn, and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-
Sleep mode, respectively. The DC1, DC2 and DC4 registers act as a write mask for the RCGCn,
SCGCn, and DCGCn registers.
In Run mode, the controller is actively executing code. In Sleep mode, the clocking of the device is
unchanged but the controller no longer executes code (and is no longer clocked). In Deep-Sleep
mode, the clocking of the device may change (depending on the Run mode clock configuration)
and the controller no longer executes code (and is no longer clocked). An interrupt returns the
device to Run mode from one of the sleep modes; the sleep modes are entered on request from
the code.
Register Map
Table 6-1 lists the System Control registers, grouped by function. All addresses given are relative
to the System Control base address of 0x400FE000.
The main oscillator checks the PLL.
The main oscillator checks the boot oscillator.
The boot oscillator divided by 64 checks the main oscillator.
System Control Register Map (Sheet 1 of 2)
Reset
0x3030011
0x70003
0x901F
-
-
Type
Preliminary
RO
RO
RO
RO
RO
Description
Device identification 0
Device identification 1
Device capabilities 0
Device capabilities 1
Device capabilities 2
March 22, 2006
See
page
52
53
55
56
57