LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 136

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

9.2.3.4
March 22, 2006
Figure 9-3.
16-Bit PWM Mode
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled
by setting the TnAMS bit in the GPTMTnMR register.
PWM mode can take advantage of the 8-bit prescaler by using the Timern Prescale Register
(GPTMTnPR) and the Timern Prescale Match Register (GPTMTnPMR). This effectively extends
the range of the timer to 24 bits.
When software writes the GPTMCTL register TnEN bit, the counter begins counting down until it
reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by
software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted
in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the Timern Match
Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 9-4 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle
assuming a 50 MHz input clock and TnPWML=0 (duty cycle would be 33% for the TnPWML=1
configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is
GPTMnMR=0x411A.
Input Signal
0xFFFF
Count
Z
Y
X
16-Bit Input Edge Time Mode Example
GPTMTnR=X
Preliminary
GPTMTnR=Y
GPTMTnR=Z
LM3S101 Data Sheet
Time
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