LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 59

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LM3S101-CRN20-XNPT

Manufacturer Part Number
LM3S101-CRN20-XNPT
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
System Control
59
Reset
Reset
Type
Type
Bit/Field
31:3
Device Capabilities 4 (DC4)
Offset 0x01C
2
1
0
RO
RO
31
15
0
0
Register 7: Device Capabilities 4 (DC4), offset 0x01C
This register is predefined by the part and can be used to verify features. It also acts as a mask for
write operations to the Run-Mode Clock Gating Control 2 (RCGC2) register (see page 77),
Sleep-Mode Clock Gating Control 2 (SCGC2) register (see page 77), and Deep-Sleep-Mode
Clock Gating Control 2 (DCGC2) register (see page 77).
RO
RO
30
14
0
0
reserved
PORTC
PORTB
PORTA
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
reserved
Reset
RO
RO
25
0
9
0
0
1
1
1
Preliminary
RO
RO
24
0
8
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this field indicates the presence of GPIO Port C.
A 1 in this field indicates the presence of GPIO Port B.
A 1 in this field indicates the presence of GPIO Port A.
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
PORTC PORTB PORTA
RO
RO
18
0
2
1
March 22, 2006
RO
RO
17
0
1
1
RO
RO
16
0
0
1

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