LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 148

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

March 22, 2006
Reset
Reset
Type
Type
GPTM Masked Interrupt Status (GPTMMIS)
Offset 0x020
31:11
RO
RO
31
15
0
0
7:4
Bit
10
9
8
3
2
1
0
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
RO
RO
30
14
0
0
TBTOMIS
TATOMIS
reserved
C2MMIS
reserved
RTCMIS
C1MMIS
C2EMIS
C1EMIS
Name
reserved
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
27
11
0
0
C2EMIS
RO
RO
26
10
0
0
Reset
0
0
0
0
0
0
0
0
0
C2MMISTBTOMIS
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPTM Capture2 Event Masked Interrupt
This is the Capture2 Event interrupt status after masking.
GPTM Capture2 Match Masked Interrupt
This is the Capture2 Match interrupt status after masking.
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
Read as 0s.
GPTM RTC Masked Interrupt
This is the RTC Event interrupt status after masking.
GPTM Capture1 Event Masked Interrupt
This is the Capture1 Event interrupt status after masking.
GPTM Capture1 Match Masked Interrupt
This is the Capture1 Match interrupt status after masking.
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RTCMIS C1EMIS C1MMISTATOMIS
RO
RO
19
0
3
0
LM3S101 Data Sheet
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
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