UPD98405 NEC, UPD98405 Datasheet - Page 12

• Manufacturer Part Number: UPD98405
• Description: 155M ATM INTEGRATED SAR CONTROLLER
• Manufacturer: NEC

1.2 Bus Interface Signals
bus interface is to be supported is selected by the PCI_MODE signal.
general I/O bus with a few circuits.
1.2.1 Generic bus interface signals (PCI_MODE pin: low level)
12
AD31-AD0
BE3_B
BE2_B
BE1_B
BE0_B
PAR3
PAR2
PAR1
PAR0
OE_B
Pin Name
The PD98405 supports a PCI bus interface or generic bus interface. Whether the PCI bus interface or generic
The PCI bus interface can be directly connected to a PCI bus. The generic bus interface can be connected to a
45, 47, 48,
3, 6, 9-12,
295-297,
300-303,
Pin No.
15-17,
34-36,
39-42,
51-54,
57-58
18
33
46
66
69
70
71
59
4
3-state
3-state
3-state
I/O
I/O
I/O
O
I
I/O Level
Data Sheet S12689EJ2V0DS00
TTL
TTL
TTL
TTL
Address/data.
These pins constitute a 32-bit address/data bus. They are
input/output pins multiplexing an address bus and a data bus.
An address is transferred at the first input/output clock. From
the second clock and onward, data is transferred. When the
high-impedance state.
Byte enable.
These pins determine the byte that becomes valid in the master
cycle of the PD98405. BE3_B corresponds to AD31 through
AD24, and BE0_B corresponds to AD7 through AD0. BE3_B
through BE0_B go into a high-impedance state when the
slave.
Bus parity.
These pins indicate the parity of AD31 through AD0. A parity
check mode is set by the GMR register. Whether the parity is
enabled or disabled, whether an odd parity or even parity is
used, and whether a word parity or byte parity is used can be
specified. When byte parity is used, PAR3 indicates the parity
of AD31 through AD24, and PAR0 indicates the parity of AD7
through AD0. In the case of word parity, PAR2 through PAR0
do not function, and PAR3 serves as an input/output pin. These
pins function as output pins when an address is output and
when data is written, and as input pins when data is read.
When the PD98405 is not accessing a bus, PAR3 through
PAR0 go into a high-impedance state. Pull up these pins when
they are not used.
Output enable.
When this pin is low, the PD98405 allows AD31 through AD0
and PAR3 through PAR0 to operate normally as three-state I/O
pins. These pins go into a high-impedance state while a high
level is input to this pin. Fix this pin to the low level in a system
where the above pins do not have to forcibly go into a high-
impedance state.
PD98405 is not accessing the bus, the AD bus goes into a
PD98405 is not accessing a bus or when it is accessing a
Function
PD98405
(1/3)