UPD98405 NEC, UPD98405 Datasheet - Page 19

• Manufacturer Part Number: UPD98405
• Description: 155M ATM INTEGRATED SAR CONTROLLER
• Manufacturer: NEC

1.3 Control Memory Interface Signals
layer device. This interface consists of a 19-bit address bus, a 32-bit data bus. The control memory of the host
system can be accessed only through this interface.
CD31-CD0
CPAR3-
CPAR0
CA18-CA0
CWE_B
COE_B
CBE3_B-
CBE0_B
INITD
Pin Name
The control memory interface is used by the PD98405 to access the external control memory and external PHY
166, 168-173,
155-159, 161
119-123,
126-130,
132-136,
139-144,
146-150,
176-181,
162-165
183-188
191-194
Pin No.
195
196
197
I/O 3-state
I/O
I/O
O
O
O
O
I
I/O Level
Data Sheet S12689EJ2V0DS00
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Control memory data.
These three-state I/O pins constitute a 32-bit data bus that is
used to transfer data to and from the control memory or PHY
layer device.
These signals are internally pulled down.
Control memory parity.
These signals indicate the parity of CD31 through CD0 every 8
bits. In the read cycle, the PD98405 checks the parity (when
enabled). In the write cycle, it outputs the parity.
These signals are internally pulled down.
Control memory address.
These signals constitute a 19-bit address bus that outputs an
address to the control memory or PHY layer device during a
read/write operation.
Control memory write enable.
This signal indicates the direction in which the control memory
is accessed.
Control memory output enable.
This signal enables or disables data output of the control
memory.
Local port byte enable.
These signals indicate the byte of the control port to be read or
written.
Initialization disable.
This signal is used to disable automatic initialization of the
control memory during chip test. Directly connect INITD to GND
during normal operation other than test.
1: Read access
0: Write access
Function
PD98405
19