UPD98405 NEC, UPD98405 Datasheet - Page 16

• Manufacturer Part Number: UPD98405
• Description: 155M ATM INTEGRATED SAR CONTROLLER
• Manufacturer: NEC

16
STOP_B
DEVSEL_B
IDSEL
REQ_B
GNT_B
PERR_B
SERR_B
INTR_B
CLK
RST_B
Pin Name
Note According to “PCI Local Bus Specification Revision 2.1”, the REQ_B pin should go into a high-impedance
state while a low level is input to the RST_B pin. The REQ_B pin of the PD98405, however, outputs a
high level.
Pin No.
294
291
288
290
289
27
24
28
29
5
Sustained
Sustained
Sustained
3-state
3-state
3-state
O
I/O
I/O
I/O
I/O
O
O
I
Note
I
I
I
open-drain
open-drain
I/O Level
Data Sheet S12689EJ2V0DS00
N-ch
N-ch
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
Stop.
This signal goes low when the target device requests the master
device to stop the current transaction.
Device select.
When the PD98405 is operating as a target, it makes this
signal low after the FRAME_B signal has been asserted active
and the PD98405 has recognized an address. When the
check to see if a target device has been selected.
Initialization device select.
This signal is high when the configuration register of the
Request.
The PD98405 makes this signal low to request the arbiter for
the bus mastership.
Grant.
This signal goes low when the arbiter grants the PD98405 the
bus mastership.
Parity error.
This signal indicates that the PD98405 has detected a data
parity error. It is enabled when the “Parity Error Response” bit of
the configuration register is set to “1”.
System error.
This signal indicates that the PD98405 has detected an
address parity error. It is enabled when both the “Parity Error
Response” and “System Error Enable” bits of the configuration
register are set to “1”.
Interrupt output.
Pull up this signal because it is an open-drain signal. INTR_B
informs the CPU that an unmasked interrupt bit of the interrupt
GSR register has been set.
Clock.
This is a system bus clock input pin. A clock of up to 33 MHz is
input.
Reset.
This signal initializes the PD98405 (on starting, etc.).
When a low level is input to RST_B, the internal state machine
and registers of the PD98405 are reset, and all the three-state
signals go into a high-impedance state. The reset input is
asynchronous. When this signal is input during operation, the
operating status at that time is lost. Keep RST_B low at least
for the duration of one clock cycle. After reset, do not access
the PD98405 for the duration of at least 20 clocks.
PD98405 is operating as a master, it samples this signal to
PD98405 is read or written.
Function
PD98405
(2/2)