UPD98405 NEC, UPD98405 Datasheet - Page 14

• Manufacturer Part Number: UPD98405
• Description: 155M ATM INTEGRATED SAR CONTROLLER
• Manufacturer: NEC

14
ABRT_B
ERR_B
SR/W_B
SEL_B
ASEL_B
CLK
RST_B
INTR_B
Pin Name
Pin No.
290
289
288
27
28
24
21
22
I/O
O
I
I
I
I
I
I
I
open-drain
I/O Level
Data Sheet S12689EJ2V0DS00
N-ch
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Abort.
This signal is used to abort a data transfer cycle. If this signal
goes low in the middle of a data transfer cycle, that cycle is
aborted, and the PD98405 resumes burst starting from the
aborted data. While a low level is input to ABRT_B, the RDY_B
signal does not function. The user can bring forward the timing
at which the PD98405 samples the RDY_B and ABRT_B
signals by 1 clock (early mode) by using an internal register
(GMR register). Pull up this pin when it is not used.
System bus error.
If an error is detected on the system bus, the device that
manages the bus uses this pin to stop the operation by the
When a low level is input to this pin, the PD98405 stops all bus
operations, sets the system bus error bit (bit 25) of the GSR
register (when not masked), and generates an interrupt. Pull up
this pin when it is not used.
Slave read/write.
This signal determines the direction of slave access.
Slave select.
This signal is asserted active (low) when slave access is
selected for the PD98405. Make sure that the SEL_B signal
goes low at the same time as or after the ASEL_B signal has
gone low. In addition, insert an inactive period of two system
clocks or more after the SEL_B signal has become inactive and
before it becomes active next time.
Slave address select.
The ASEL_B signal selects the direct address register of the
When a low level is input to ASEL_B, the PD98405 samples
the AD bus at the first rising edge of CLK.
Clock.
This is a system bus clock input pin. A clock of up to 33 MHz
can be input.
The RST_B signal initializes the PD98405 (on starting). After
reset, the PD98405 can start normal operation. When a low
level is input to RST_B, the internal state machine and registers
of the PD98405 are reset, and all the three-state signals go
into a high-impedance state. Reset input is asynchronous. If it
is input during operation, the operation status at that time is lost.
Keep RST_B low at least for the duration of one clock cycle.
Interrupt output.
Pull up this signal because it is an open-drain signal.
This signal informs the CPU that an unmasked interrupt bit of
the interrupt GSR register has been set.
Reset.
PD98405.
PD98405.
1: Read access
0: Write access
Function
PD98405
(3/3)