UPD98405 NEC, UPD98405 Datasheet - Page 21

• Manufacturer Part Number: UPD98405
• Description: 155M ATM INTEGRATED SAR CONTROLLER
• Manufacturer: NEC

1.5 JTAG Boundary Scan Signals
1.6 Other Signals
JDI
JDO
JMS
JCK
JRST_B
SCLK
PCI_MODE
TEST
Pin Name
Pin Name
Remark This function can be supported upon request.
These signals conform to IEEE1149.1 JTAG Boundary-Scan Standard.
Pin No.
Pin No.
285
284
283
282
281
198
118
271
3-state
I/O
I/O
O
I
I
I
I
I
I
I
I/O Level
I/O Level
Data Sheet S12689EJ2V0DS00
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Boundary scan data input.
Connect this pin to ground when it is not used.
Boundary scan data output.
Open this pin when it is not used.
Boundary scan mode select.
Connect this pin to ground when it is not used.
Boundary scan clock input.
Connect this pin to ground when it is not used.
Boundary scan reset.
Connect this pin to ground when it is not used.
SAR system clock.
This pin supplies a clock for a SAR block operation.
The maximum clock frequency is 25 MHz.
PCI/generic bus mode.
This pin selects PCI or generic bus mode.
Internal test pin.
Open this pin. When a high level is input to this pin, the test
mode is selected.
This signal is internally pulled down.
The test mode is used for internal testing and cannot be used by
the user.
0: Generic bus mode
1: PCI bus mode
Function
Function
PD98405
21