AN2768 Freescale Semiconductor / Motorola, AN2768 Datasheet - Page 14

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AN2768

Manufacturer Part Number
AN2768
Description
Implementation of a 128-Point FFT on the MRC6011 Device
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
The FFT on the MRC6011 Device
After the 128 real numbers are transposed and transferred into the R[8–15] registers of the RC array, the 128
imaginary numbers are read from the frame buffer to repeat the same transpose operations in registers R[0–7]. At
this time, both the real and imaginary parts have completed the bit reversal. However, the 128 × 2 = 256 data items
occupy all 16 (registers/cell) × 16 cells = 256 registers in the RC array, leaving no room for further operations. To
continue with subsequent butterfly operations, we can keep only half of the transposed (or bit reversed) data in the
RC array and move half of the data out to the frame buffer for temporary storage, making 128 registers available
for butterfly operations.
The bit reversed data is organized into groups of 16 complex samples to form eight groups of data. Groups 1 to 4
are selected to stay in the RC registers, and Groups 5 to 8 are temporarily placed into the frame buffer.
14
MORPHO{//5.cycle
}
MORPHO{//6.cycle
}
MORPHO{//7.cycle
}
MORPHO{//8.cycle
}
Implementation of a 128-Point FFT on the MRC6011 Device, Rev. 0
CELL{*,0}:R2 R12=BYP{R0{*,4}};//Expr lane right->left
CELL{*,1}:R3 R13=BYP{R1{*,5}};//Expr lane right->left
CELL{*,2}:R6 R8 =BYP{R2{*,0}};
CELL{*,3}:R7 R9 =BYP{R3{*,1}};
CELL{*,4}:R0 R14=BYP{R4{*,6}};
CELL{*,5}:R1 R15=BYP{R5{*,7}};
CELL{*,6}:R4 R10=BYP{R6{*,2}};//Expr lane left->right
CELL{*,7}:R5 R11=BYP{R7{*,3}};//Expr lane left->right
CELL{*,0}:R4
CELL{*,1}:R5
CELL{*,2}:R0
CELL{*,3}:R1
CELL{*,4}:R6
CELL{*,5}:R7
CELL{*,6}:R2
CELL{*,7}:R3
CELL{*,0}:R5
CELL{*,1}:R4
CELL{*,2}:R1
CELL{*,3}:R0
CELL{*,4}:R7
CELL{*,5}:R6
CELL{*,6}:R3
CELL{*,7}:R2
CELL{*,0}:R3
CELL{*,1}:R2
CELL{*,2}:R7
CELL{*,3}:R6
CELL{*,4}:R1
CELL{*,5}:R0
CELL{*,6}:R5
CELL{*,7}:R4
R10=BYP{R0{*,2}};
R11=BYP{R1{*,3}};
R14=BYP{R2{*,6}};//Expr lane right->left
R15=BYP{R3{*,7}};//Expr lane right->left
R8 =BYP{R4{*,0}};//Expr lane left->right
R9 =BYP{R5{*,1}};//Expr lane left->right
R12=BYP{R6{*,4}};
R13=BYP{R7{*,5}};
R11=BYP{R0{*,3}};
R10=BYP{R1{*,2}};
R15=BYP{R2{*,7}};//Expr lane right->left
R14=BYP{R3{*,6}};//Expr lane right->left
R9 =BYP{R4{*,1}};//Expr lane left->right
R8 =BYP{R5{*,0}};//Expr lane left->right
R13=BYP{R6{*,5}};
R12=BYP{R7{*,4}};
R13=BYP{R0{*,5}};//Expr lane right->left
R12=BYP{R1{*,4}};//Expr lane right->left
R9 =BYP{R2{*,1}};
R8 =BYP{R3{*,0}};
R15=BYP{R4{*,7}};
R14=BYP{R5{*,6}};
R11=BYP{R6{*,3}};//Expr lane left->right
R10=BYP{R7{*,2}};//Expr lane left->right
Freescale Semiconductor

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