AN2768 Freescale Semiconductor / Motorola, AN2768 Datasheet - Page 7

• Manufacturer Part Number: AN2768
• Description: Implementation of a 128-Point FFT on the MRC6011 Device
• Manufacturer: Freescale Semiconductor / Motorola

the six-core MRC6011 device delivers a peak performance of 24 giga complex correlations per second with a
sample resolution of 8 bits for I and Q inputs each–or up to 48 giga complex correlations per second at a resolution
of 4 bits.
The Freescale RCF technology is designed to meet the processing needs of computationally intensive tasks such as
the FFT. The Freescale MRC6011 RCF device is a highly effective device on which to implement the FFT. The
RCF core technology of the MRC6011 device is based on an array of processing elements that combines efficient
parallel computing with fast and flexible reconfiguration and data routing. Figure 7 shows the highly parallel
architecture of the RCF core. The array of processors perform DSP-like operations for compute intensive
algorithms in many applications. The RCF core contains the array of reconfigurable cells (RCs), the RC controller,
a context memory that acts as the RC program memory, and a frame buffer that is the data memory of the RC array.
The data and instruction memory of the RC controller resides outside the RCF core and is associated with an
ICache and a DCache. The sequence generator and interleaver interact only with other internal core components
and are designed for CDMA operations. The input buffer receives data from outside with a 32-bit input bus, and the
DMA controller handles all other data and RC array program transfers from external memory space. Multiple cores
can interconnect via internal and external buses to expand the RCF parallelism with arbitrators and glue logic.
Multiple cores can perform more parallel computations with careful programming of the shared resources.
Freescale Semiconductor
Input
32
DMA
Bus
Bus
128
Sequence
Generator
Controller
Buffer
Input
DMA
38
128
Frame
Buffer
Implementation of a 128-Point FFT on the MRC6011 Device, Rev. 0
Memory
Context
Figure 7. RCF Core with 8 × 2 Reconfigurable Cells
128
Data in Rows of 128 Bits
(0,0)
(1,0)
Cell
Cell
Interleaver
(1,1)
(0,1)
Cell
Cell
(0,2)
(1,2)
RC Controller
Cell
Cell
(0,3)
Cell
(1,3)
Cell
RC Array
(1,4)
(0,4)
Cell
Cell
Cache
MRC6011 Architecture Overview
Data
(0,5)
(1,5)
Cell
Cell
Memory Controller
Instruction
Cache
(0,6)
(1,6)
Cell
Cell
(0,7)
Controller
Cell
(1,7)
Cell
Bus
32
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