AN2768 Freescale Semiconductor / Motorola, AN2768 Datasheet - Page 8

• Manufacturer Part Number: AN2768
• Description: Implementation of a 128-Point FFT on the MRC6011 Device
• Manufacturer: Freescale Semiconductor / Motorola

MRC6011 Architecture Overview
The RC controller executes the main control process of an application and schedules every execution cycle of the
processing array. The actual array instructions reside in the context memory. The wide interconnect path between
the context memory and the RC array allows single-cycle reconfiguration of the processing units. The DMA
controller is the interface to the main system bus. The input buffer connects to the antenna input ports and
appropriately interleaves and combines the data for efficient writes into the frame buffer. The following sections
describe the frame buffer and RC array to clarify how parallel FFT butterflies are performed on this architecture.
2.1 Frame Buffer
The frame buffer is a dual-port RAM that connects one side to the RC controller, RC array, and interleaver, and the
other side to the DMA controller, input buffer, and sequence generator via a separate 128-bit bus. The frame buffer
is organized in rows (horizontally) and banks (vertically) to facilitate easy data transfer to and from the RC array.
Since the RC array is organized into two rows of eight RCs each, there are eight two-byte banks in the frame buffer.
As shown in Figure 8, an Omega network between the frame buffer and the RC array routes data into the RC array
for computation in each RC. The Omega network can broadcast a byte or a 16-bit word into all RCs so that all RCs
process the same data. Alternatively, the Omega network can transfer a row of data into the RCs column-wise so
that each RC processes different data. The 128-point FFT application employs both of these data routing
mechanisms.
The 40 KB frame buffer is organized into 2560 rows × 16 bytes per row. In the 128-point FFT computation, input
data and twiddle factors are both 16-bit integers or 16-bit fixed-point numbers (–1.0 to +1.0), so there are eight
input data or twiddle factors in each frame buffer row. Section 3 describes how the entire 128 complex data input
samples and the various twiddle factors are stored to support parallel butterfly operations on the RC array.
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D(n+1,0)
D(n+1,0)
D(n,5)
D(n+1,1)
RC0
D(n+1,1)
D(n,6)
D(n+1,2)
D(n+1,2)
D(n,7)
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RC1
D(n+1,3)
Implementation of a 128-Point FFT on the MRC6011 Device, Rev. 0
D(n,8)
D(n+1,4)
D(n+1,4)
D(n,9)
RC2
D(n,5)
Figure 8. Omega Network Location
D(n,5)
D(n,10)
D(n,6)
D(n,6)
D(n,11)
RC3
D(n,7)
Ω Network
D(n,7)
Frame Buffer
D(n,12)
D(n,8)
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RC4
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RC5
D(n,11)
D(n+1,0)
D(n,12)
D(n,12)
D(n+1,1)
Freescale Semiconductor
D(n,13)
RC6
D(n,13)
D(n+1,2)
D(n,14)
D(n,14)
D(n+1,3)
D(n,15)
RC7
D(n,15)
D(n+1,4)