AN2768 Freescale Semiconductor / Motorola, AN2768 Datasheet - Page 26

• Manufacturer Part Number: AN2768
• Description: Implementation of a 128-Point FFT on the MRC6011 Device
• Manufacturer: Freescale Semiconductor / Motorola

Performance and Error Analysis
• The right 1 bit shift at the end of the R13, R12 addition.
• Two additional multiplication cycles to scale down R4 and R0 for adjustment.
• One NOP cycle as a result of the MAC delay introduced by the multiplication preceding it.
• Instead of holding the constant of 0x2, the R15 register retains the constant of 0x1 throughout the butterfly stages
4.3 Rounding on RC
Although rounding on RCF is not automatic, it is achieved by adding 0x00008000 to or subtracting 0xFFFF8000
from the number to be rounded. In Figure 23, the truncation and rounding operations are directly compared. The
net effect of the truncation introduces bias or error in the final result. However, proper rounding generally yields an
unbiased result or a near zero bias in the final result. An apparent cost of rounding is the need for locations to hold
the rounding constant as well as the intentional multiplication with a constant (one) and add operation if no
multiplication is necessary in the original operations.
5
This section presents performance data of the implementation, including RCF cycles counts, frame buffer memory
requirements, context memory usage, and averaged errors of the FFT spectra. We used both white noise and sine
wave as test vectors to test the implementation. The errors associated with each test vector are stable and
acceptable with improved precision. With 8-bit inputs, the errors would have been much larger.
Table 4 lists the cycle counts for different runs of the FFT. FFT execution time on RCF is calculated as 3659cyc ×
4ns = 14.636 µs, 684 cyc × 4 ns = 2.736 µs at 250 MHz RCF core frequency.
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due to the scale down operation.
Performance and Error Analysis
CELL{*,*} R14 = INV{ZERO} << 15;
CELL{*,*} R2 = MULSIH{R0,R1,R14} << 1;
Truncation
Rounding
R2 = MAC_REG [ ( (R0 × R1) << 1) – sign extend (R14) ]
Figure 23. Comparison of Truncation and Rounding Operations on RCF
Implementation of a 128-Point FFT on the MRC6011 Device, Rev. 0
MAC_REG [ ( (R0 × R1) << 1) – 0xFFFF8000 ]
MAC_REG [ ( (R0 × R1) << 1) + 0x00008000 ]
Output
Output
32 Bits
0 1
0 1
0 1
1 0
+
||
Throw Away
Throw Away
/* move 0x8000 into R14 */
/* multiply R0,R1 and round */
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[31 . . . 16]
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