AN2768 Freescale Semiconductor / Motorola, AN2768 Datasheet - Page 9

• Manufacturer Part Number: AN2768
• Description: Implementation of a 128-Point FFT on the MRC6011 Device
• Manufacturer: Freescale Semiconductor / Motorola

2.2 RC Array
The 16-element RC array operates using the same clock as the RC controller that schedules array operations. Each
RC can complete a MAC operation, so the array performs a maximum of 16 MACs on each core clock cycle. The
RC array takes data directly from the frame buffer through the Omega network to perform operations on data
already in the RC registers. Depending on the application, the intermediate results are either temporarily stored in
one of the sixteen registers in each RC or they are output back to the frame buffer rows for subsequent computing.
Sometimes, data exchange between two or more cells is needed. Sophisticated inter-cell connections enable the
cells to exchange data items in selected rule-governed ways to feed data to locations where it is needed on the next
clock cycle. In the 128-point FFT application, with decimation in time, the bit reversal of the input data requires
this type of operation to generate the 128-point complex frequency components in normal order.
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The 128-point complex input samples are 16-bit two’s complement fixed-point real and imaginary numbers with a
value between –1.0 and +1.0 and in the following format:
Since the frame buffer is organized into 128-bit rows, each row can store eight 16-bit real or eight 16-bit imaginary
numbers. For complex numbers, the first row usually stores the real parts and the next row stores the imaginary
parts, as shown in Table 2.
Alternatively, the real parts and the imaginary parts can be grouped together and occupy consecutive rows if they
are to be accessed one after the other. We choose this type of storage over the one shown in Table 2 for the
following reasons:
• Reading consecutive rows of real or imaginary numbers into RC registers is simple. Conveniently, the input data
• The twiddle factors are not loaded into the RC registers for the butterfly operations. It is more efficient if real
3.1 Input Data Storage in the Frame Buffer
The 128 complex input samples are stored so that 128 real numbers occupy 16 rows of the frame buffer and 128
imaginary numbers occupy another 16 rows of the frame buffer, as illustrated in Figure 9.
Freescale Semiconductor
is transposed for bit reversal in the RC registers.
parts of the twiddle factors are collocated in consecutive rows of the frame buffer.
Sign Bit
The FFT on the MRC6011 Device
Data[0].im
Data[0].re
Bytes 0/1
Bit
Table 2. Conventional Data Storage in the Frame Buffer for Complex Numbers
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2/3
Data[1].re
Data[1].im
S
Implementation of a 128-Point FFT on the MRC6011 Device, Rev. 0
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Data[2].re
Data[2].im
Radix Point
12
11
6/7
Data[3].re
Data[3].im
10
9
8/9
Data[4].re
Data[4].im
8
7
10/11
Data[5].re
Data[5].im
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The FFT on the MRC6011 Device
12/13
Data[6].re
Data[6].im
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Data[7].re
Data[7].im
2
1
0
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