LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 11

• Manufacturer Part Number: LM3S5652
• Description: Lm3s5652 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Figure 15-9.
Figure 15-10. MICROWIRE Frame Format (Single Frame) .................................................................... 426
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 427
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 427
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 16-4.
Figure 16-5.
Figure 16-6.
Figure 16-7.
Figure 16-8.
Figure 16-9.
Figure 16-10. Master Burst RECEIVE .................................................................................................. 465
Figure 16-11. Master Burst RECEIVE after Burst SEND ........................................................................ 466
Figure 16-12. Master Burst SEND after Burst RECEIVE ........................................................................ 467
Figure 16-13. Slave Command Sequence ............................................................................................ 468
Figure 17-1.
Figure 17-2.
Figure 18-1.
Figure 19-1.
Figure 19-2.
Figure 19-3.
Figure 20-1.
Figure 23-1.
Figure 23-2.
Figure 23-3.
Figure 23-4.
Figure 23-5.
Figure 23-6.
Figure 23-7.
Figure 23-8.
Figure 23-9.
Figure 23-10. Power-On Reset Timing ................................................................................................. 658
Figure 23-11. Brown-Out Reset Timing ................................................................................................ 658
Figure 23-12. Software Reset Timing ................................................................................................... 658
Figure 23-13. Watchdog Reset Timing ................................................................................................. 658
Figure 24-1.
June 02, 2008
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 425
I
I
START and STOP Conditions ......................................................................................... 458
Complete Data Transfer with a 7-Bit Address ................................................................... 459
R/S Bit in First Byte ........................................................................................................ 459
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 462
Master Single RECEIVE ................................................................................................. 463
Master Burst SEND ....................................................................................................... 464
CAN Module Block Diagram ........................................................................................... 493
CAN Bit Time ................................................................................................................ 500
USB Module Block Diagram ........................................................................................... 533
Analog Comparator Module Block Diagram ..................................................................... 623
Structure of Comparator Unit .......................................................................................... 624
Comparator Internal Reference Structure ........................................................................ 625
64-Pin LQFP Package Pin Diagram ................................................................................ 634
Load Conditions ............................................................................................................ 650
I
Hibernation Module Timing ............................................................................................. 654
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 654
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 655
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 655
JTAG Test Clock Input Timing ......................................................................................... 656
JTAG Test Access Port (TAP) Timing .............................................................................. 656
External Reset Timing (RST) .......................................................................................... 657
64-Pin LQFP Package ................................................................................................... 659
2
2
2
C Block Diagram ......................................................................................................... 457
C Bus Configuration .................................................................................................... 458
C Timing ..................................................................................................................... 653
Preliminary
2
C Bus ............................................................... 459
LM3S5652 Microcontroller
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