LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 18

• Manufacturer Part Number: LM3S5652
• Description: Lm3s5652 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Register 17:
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Register 24:
Register 25:
Register 26:
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 375
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Register 2:
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Register 21:
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Register 25:
Register 26:
Synchronous Serial Interface (SSI) ............................................................................................ 418
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
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Register 9:
Register 10:
18
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 369
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 369
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 369
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 369
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 370
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 370
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 371
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 371
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 373
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 374
UART Data (UARTDR), offset 0x000 ............................................................................... 384
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 386
UART Flag (UARTFR), offset 0x018 ................................................................................ 388
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 390
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 391
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 392
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 393
UART Control (UARTCTL), offset 0x030 ......................................................................... 395
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 397
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 399
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 401
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 402
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 403
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 405
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 406
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 407
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 408
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 409
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 410
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 411
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 412
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 413
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 414
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 415
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 416
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 417
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 431
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 433
SSI Data (SSIDR), offset 0x008 ...................................................................................... 435
SSI Status (SSISR), offset 0x00C ................................................................................... 436
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 438
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 439
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 441
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 442
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 443
SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 444
Preliminary
June 02, 2008