LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 611

• Manufacturer Part Number: LM3S5652
• Description: Lm3s5652 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Type
USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1)
Base 0x4005.0000
Offset 0x304
Type R/W, reset 0x0000
June 02, 2008
Host
Bit/Field
15:0
R/W
15
0
R/W
Register 84: USB Request Packet Count in Block Transfer Endpoint 1
(USBRQPKTCOUNT1), offset 0x304
Register 85: USB Request Packet Count in Block Transfer Endpoint 2
(USBRQPKTCOUNT2), offset 0x308
Register 86: USB Request Packet Count in Block Transfer Endpoint 3
(USBRQPKTCOUNT3), offset 0x30C
This 16-bit read/write register is used in Host mode to specify the number of packets that are to be
transferred in a block transfer of one or more bulk packets to receive endpoint n. The core uses the
value recorded in this register to determine the number of requests to issue where the AUTORQ bit
in the USBRXCSRHn register has been set. See “IN Transactions as a Host” on page 540.
Note:
14
0
R/W
13
0
COUNT
Name
Multiple packets combined into a single bulk packet within the FIFO count as one packet.
R/W
12
0
R/W
11
0
Type
R/W
R/W
10
0
R/W
Reset
0x00
9
0
Preliminary
R/W
8
0
COUNT
Description
Block Transfer Packet Count
Sets the number of packets of size MaxP that are to be transferred in
a block transfer.
Note:
R/W
7
0
This is only used in Host mode when AUTORQ is set. The bit
has no effect in Device mode or when AUTORQ is not set.
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
LM3S5652 Microcontroller
R/W
2
0
R/W
1
0
R/W
0
0
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