LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 441

• Manufacturer Part Number: LM3S5652
• Description: Lm3s5652 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
Offset 0x018
Type RO, reset 0x0000.0008
June 02, 2008
Bit/Field
31:4
RO
RO
3
2
1
0
31
15
0
0
RO
RO
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
30
14
0
0
RO
RO
29
13
reserved
RORRIS
0
0
RXRIS
RTRIS
TXRIS
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
reserved
RO
RO
Reset
25
0x00
0
9
0
1
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
TXRIS
RO
RO
19
0
3
1
LM3S5652 Microcontroller
RXRIS
RO
RO
18
0
2
0
RTRIS
RO
RO
17
0
1
0
RORRIS
RO
RO
16
0
0
0
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