LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 113

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

July 5, 2006
Reset
Reset
Type
Type
GPIO Data (GPIODATA)
Offset 0x000
RO
RO
31
15
0
0
31:8
7:0
Bit
Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 114).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived
from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask
cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask
cause the corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
RO
RO
30
14
0
0
reserved
Name
DATA
RO
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
Type
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPIO Data
This register is virtually mapped to 256 locations in the address
space. To facilitate the reading and writing of data to these
registers by independent drivers, the data read from and the data
written to the registers are masked by the eight address lines
ipaddr[9:2]
state. Writes to this register only affect bits that are not masked
by
Register Operation” on page 107 for examples of reads and
writes.
RO
RO
24
0
8
0
ipaddr[9:2]
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
. Reads from this register return its current
and are configured as outputs. See “Data
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
DATA
R/W
RO
19
0
3
0
LM3S301 Data Sheet
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
113